RISC V Assembler, Disassembler, and Simulation Environment (first release)

RISC V Assembler
This is the first release of a RISC V Assembler. RISC V is a new, open source, CPU design.

For more information about this project, download the zip file at this link, and read the readme.txt document.

The long term goal of this project is to create a RISC V development environment for student learning, much like the MARS or SPIM environments for MIPS.

The students who did this project were John Lewis, Rachael Birky, Logan Turske as a project for the Johns Hopkins CS611 class in the Spring of 2018.