OneAddress CPU

This book covers the implementation a One Address (Accumulator) Harvard Architure CPU in Logisim. It is a full CPU with memory access, ALU, and branching, and real programs can be written in it. However there is no I/O, so answers must be read from memory or registers. Included with this CPU is a simple 2-pass assembler, and the book covers all the major topics in creating a simple CPU (assembly language, machine code, assembler, and CPU).

Because it is actually implemented in Logisim, the CPU can be modified and problems given where the students must modify the CPU and the assembler. This makes it an interesting toy CPU that can be used for problems in a Computer Organization course.

The CPU was originally written on a dare when I told another professor that I could implement a OneAddress CPU in less than a day. The original CPU (before it was cleaned up) actuall took less than 4 hours, which speaks to its simplicity. The instruction set is minimal, and the machine code is so clean that students often write their programs to test CPU modifications before implementing the instructions in the assembler.

The original idea was for this CPU to be extended to CPU architectures (e.g. 0, 2-3 Addresses, and Von Neumann achitectures). These have been student projects in my Johns Hopkins Hardware class (EN.605.611).

Note that the link is the main site for this book. At the link are two downloads. The first is the text of the book in pdf format. The second is a zip file of resources for the book, including all Logisim circuit for the CPU, the assembler, example programs, and the original Word file if you want to change it.